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HSDL-3220
IrDA(R) Data Compliant Low Power 4.0 Mbit/s Infrared Transceiver
Data Sheet
Description The HSDL-3220 is a new generation low profile high speed infrared transceiver module that provides interface between logic and IR signals for throughair, serial, half-duplex IR data-link. The module is fully compliant to IrDA Physical Layer specification version 1.4 low power from 9.6kbit/s to 4.0 Mbit/s (FIR) and is IEC825-Class 1 Eye Safe. The HSDL-3220 can be shutdown completely to achieve very low power consumption. In the shutdown mode, the PIN diode will be inactive and thus producing very little photocurrent even under very bright ambient light. It is also designed to interface to input/ output logic circuits as low as 1.8V. These features are ideal for mobile devices that require low power consumption.
VCC CX4 CX1 IOVCC (7) VCC (6) GND (8) CX2
Features
* Fully compliant to IrDA 1.4 physical layer low power specification from 9.6 kbit/s to 4.0 Mbit/s (FIR) * Miniature package - Height: 2.5 mm - Width: 8.0 mm - Depth: 3.0 mm * Typical link distance > 50 cm * Guaranteed temperature performance, -25o to 70oC * Critical parameters are guaranteed over temperature and supply voltage * Low power consumption - Low shutdown current - Complete shutdown of TXD, RXD, and PIN diode * Excellent EMI performance * Vcc supply 2.7 to 3.6 Volts * Interfacing with I/O logic circuits as low as 1.8 V * Lead-free package * LED stuck-high protection * Designed to accommodate light loss with cosmetic windows * IEC 825-class 1 eye safe * Lead-free and RoHS Compliant
HSDL-3220
SD (5)
RECEIVER
RXD (4)
Applications
* Mobile telecom - Mobile phones - Smart phones - Pagers * Data communication - Pocket PC handheld products - Personal digital assistants - Portable printers * Digital imaging - Digital cameras - Photo-imaging printers * Electronic wallet * Small industrial & medical instrumentation - General data collection devices - Patient & pharmaceutical data collection devices
SHIELD
TXD (3) LED C (2)
TRANSMITTER
R1
Vled
LED A (1)
CX3
Figure 1. Functional block diagram of HSDL-3220.
8
7
6
5
4
3
2
1
Figure 2. Rear view diagram with pinout.
Application Support Information The Application Engineering Group is available to assist you with the application design Order Information Part Number
HSDL-3220-021 HSDL-3220-001
associated with the HSDL-3220 infrared transceiver module. You can contact them through your local sales representatives for additional details.
Marking Information The unit is marked with the letter "G" and "YWWLL" on the shield where: Y is the last digit of the year WW is the work week LL is the lot information
Packaging Type
Tape and Reel Tape and Reel
Package
Front View Front View
Quantity
2500 500
I/O Pins Configuration Table Pin
1 2 3 4 5 6 7 8 -
Symbol
LED A LED C TXD RXD SD Vcc IOVcc GND Shield
Description
LED Anode LED Cathode Transmit Data. Active High. Receive Data. Active Low. Shutdown. Active High. Supply Voltage Input/Output ASIC Vcc Ground EMI Shield
I/O Type
I
Notes
1 2
I O I
3 4 5 6 7 8 9
Recommended Application Circuit Components Component
R1
Recommended Value
5.6 5%, 0.25 watt for 2.7 Vled < 3.3V 10 5%, 0.25 watt for 3.3 Vled < 4.2V 15 5%, 0.25 watt for 4.2 Vled < 5.5V 0.47 F 20%, X7R Ceramic 6.8 F 20%, Tantalum
Notes
CX1, CX4 CX2, CX3
10 11
Notes: 1. Tied through external series resistor, R1, to regulated Vled from 2.7 to 5.5V. Please refer to table above for recommended series resistor value. 2. Internally connected to LED driver. Leave this pin unconnected. 3. This pin is used to transmit serial data when SD pin is low. If this pin is held high for longer than 50 s, the LED is turned off. Do NOT float this pin. 4. This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. The pin is in tri-state when the transceiver is in shutdown mode. The receiver output echoes transmitted signal. 5. The transceiver is in shutdown mode if this pin is high for more than 400 s. On falling edge of this signal, the state of the TXD pin sampled and used to set receiver low bandwidth (TXD=low) or high bandwidth (TXD=high) mode. Refer to the section "Bandwidth selection timing" for programming information. Do NOT float this pin. 6. Regulated, 2.7 to 3.6 Volts. 7. Connect to ASIC logic controller Vcc voltage or supply voltage. The voltage at this pin must be equal to or less than supply voltage. 8. Connect to system ground. 9. Connect to system ground via a low inductance trace. For best performance, do not connect directly to the transceiver pin GND. 10. CX1 must be placed within 0.7 cm of the HSDL-3220 to obtain optimum noise immunity. 11. In environments with noisy power supplies, including CX2, as shown in Figure 1, can enhance supply ripple rejection performance.
2
Bandwidth Selection Timing The transceiver is in default SIR/ MIR mode when powered on. User needs to apply the following programming sequence to both the SD and TXD inputs to enable the transceiver to operate at FIR mode.
VIH SD/MODE
VIL tS tH
VIH SD/MODE 50%
50% VIL tS tH VIH
TXD
50%
50% VIL
TXD
50%
50% VIL
Figure 3. Bandwidth selection timing at SIR/MIR mode.
Figure 4. Bandwidth selection timing at FIR mode.
Setting the transceiver to SIR/MIR Mode (9.6 kbit/s to 1.152 Mbit/s) 1. Set SD/Mode input to logic HIGH 2. TXD input should remain at logic LOW 3. After waiting for tS 25 ns, set SD/Mode to logic LOW, the HIGH to LOW negative edge transition will determine the receiver bandwidth
4. Ensure that TXD input remains low for tH 100 ns, the receiver is now in SIR/MIR mode 5. SD input pulse width for mode selection should be > 50 ns. Setting the transceiver to FIR (4.0 Mbit/s) Mode 1. Set SD/Mode input to logic HIGH
2. After SD/Mode input remains HIGH at > 25 ns, set TXD input to logic HIGH, wait tS 25 ns (from 50% of TXD rising edge till 50% of SD falling edge) 3. Then set SD/Mode to logic LOW, the HIGH to LOW negative edge transition will determine the receiver bandwidth 4. After waiting for tH 100 ns, set the TXD input to logic LOW 5. SD input pulse width mode selection should be > 50 ns.
Transceiver I/O Truth Table Inputs TXD
High Low Low Don't Care
Outputs SD
Low Low Low High
Light Input to Receiver
Don't Care High Low Don't Care
LED
On Off Off Off
RXD
Not Valid Low High High
Note
12,13
Notes: 12. In-band IrDA signals and data rates 4.0 Mbit/s 13. RXD logic low is a pulsed response. The condition is maintained for a duration dependent on pattern and strength of the incident intensity.
3
CAUTIONS: The BiCMOS inherent to the design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Absolute Maximum Ratings For implementations where case to ambient thermal resistance is 50C/W. Parameter
Storage Temperature
Symbol
TS TA VLEDA VCC VI VO ILED (DC) ILED (PK)
Min.
-40 -25 0 0 0 0
Max.
+100 +70 6.5 6.5 6.5 6.5 50 200
Units
C C V V V V mA mA
Conditions
Operating Temperature LED Anode Voltage Supply Voltage Input Voltage: TXD, SD/Mode Output Voltage: RXD DC LED Transmit Current Average Transmit Current
90 s pulse width 25% duty cycle
Recommended Operating Conditions Parameter
Supply Voltage Input/Output Voltage Logic Input Voltage for TXD, SD/Mode Logic High Logic Low Logic High Receiver Input Irradiance EIH, max Logic Low LED (Logic High) Current Pulse Amplitude Receiver Data Rate EIL ILEDA 0.0096 150 4.0
Symbol
VCC IOVcc VIH VIL EIH, min
Min.
2.7 1.8 IOVcc - 0.5 0
Typ.
Max.
3.6 Vcc IOVcc 0.4 0.0081 0.020 500 0.3
Units
V V V V mW/cm2 mW/cm2 mW/cm2 W/cm2 mA Mbit/s
Conditions
9.6kbit/s in-band signals 1.152 Mbit/s [14] 1.152 Mbit/s < in-band signals 4.0 Mbit/s [14] 9.6 kbit/s in-band signals 4.0 Mbit/s[14]
For in-band signals [14]
Note : 14. An in-band optical signal is a pulse/sequence where the peak wavelength, p, is defined as 850 p 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4.
4
Electrical and Optical Specifications Specifications (Min. and Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25C, Vcc set to 3.0V and IOVcc set to 1.8V unless otherwise noted.
Parameter
Receiver Viewing Angle Peak Sensitivity Wavelength RXD Output Voltage Logic High Logic Low RXD Pulse Width (SIR)[15] RXD Pulse Width (MIR)[16] RXD Pulse Width (FIR) [16] RXD Rise and Fall Times Receiver Latency Time[17] Receiver Wake Up Time[18] Transmitter Radiant Intensity Viewing Angle Peak Wavelength Spectral Line Half Width TXD Input Current LED ON Current TXD Pulse Width (SIR) TXD Pulse Width (MIR) TXD Pulse Width (FIR) Maximum Optical PW[19] TXD Rise and fall Time (Optical) LED Anode On-State Voltage Transceiver Supply Current Shutdown Idle ICC1 ICC2 0.1 1.8 1 3.0 A mA VSD VIH, Ta= 25C VSD VIL, VTXD VIL, EI=0 High Low IEH 2 p IH IL ILEDA tPW (SIR) tPW(MIR) tPW(FIR) tPW(max.) tr, tf VON(LEDA) 1.6 1.5 148 115 150 1.6 217 125 50 1.8 260 135 100 600 40 2.1 10 30 875 35 10 10 45 60 mW/sr nm nm A A mA s ns ns s ns ns V tPW(TXD) = 1.4 s at 115.2 kbit/s tPW (TXD) = 125 ns at 4.0 Mbit/s ILEDA=150 mA, VTXD VIH VTXD VIH 0 VTXD VIL VTXD VIH, R1=5.6ohm, Vled=3.0V tPW (TXD) = 1.6 s at 115.2 kbit/s tPW (TXD) = 217 ns at 1.152 Mbit/s tPW(TXD)=125 ns at 4.0 Mbit/s ILEDA= 150 mA, 15, VTXD VIH, VSD VIL, Ta=25C 2 p VOH VOL tPW (SIR) tPW(MIR) tPW(FIR) tr, tf tL tW IOVCC - 0.2 0 1 100 80 60 25 50 50 100 30 880 IOVCC 0.4 4.0 500 175 nm V V s ns ns ns s s IOH = -200 A, EI 0.3 W/cm2 IOL = 200 A, EI 8.1 W/cm2 15, CL = 9 pF 15, CL = 9 pF 15, CL = 9 pF CL = 9 pF
Symbol
Min.
Typ.
Max.
Units
Conditions
Notes: 15. For in-band signals from 9.6 kbit/s to 115.2 kbit/s, where 9 W/cm2 EI 500 mW/cm2. 16. For in-band signals from 0.576 Mbit/s to 4.0 Mbit/s, where 22.5 W/cm2 EI 500 mW/cm2. 17. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity. 18. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output. 19. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED for eye safety protection.
5
tpw
tpw VOH 90% 50% 10%
LED ON 90% 50% 10% LED OFF
tf tr
VOL
tr
tf
Figure 5. RxD output waveform.
Figure 6. LED optical waveform.
SD
TXD
RX LIGHT
LED
RXD
tpw (MAX.)
tRW
Figure 7. TxD "Stuck On" protection waveform.
Figure 8. Receiver wakeup time waveform.
120
2.4
RADIANT INTENSITY (mW/sr)
100 80 60 40 20 0 0.10
VLEDA (V)
2.2
2.0
1.8
1.6
0.15
0.20
0.25
0.30
0.35
1.4 0.10
0.15
0.20
0.25
0.30
0.35
ILEDA (A)
ILEDA (A)
Figure 9. Radiant Intensity vs ILEDA.
Figure 10. VLEDA vs ILEDA.
6
HSDL-3220 Package Dimensions
2.0
0.8
0.4
7
HSDL-3220 Tape and Reel Dimensions
4.0 0.1 Unit: mm O1.5 +0.1 0 POLARITY Pin 8: VLED 7.5 0.1 16.0 0.2 1.5 0.1 1.75 0.1
Pin 1: GND 0.4 0.05 2.8 0.1
8.4 0.1 3.4 0.1 8.0 0.1 Progressive Direction
Empty (40 mm min)
Parts Mounted
Leader (400 mm min)
Empty (40 mm min)
Option # "B" "C" Quantity 001 178 60 500 021 330 80 2500
Unit: mm
Detail A 2.0 0.5 13.0 0.5 B C
R1.0 LABEL 21 0.8
Detail A
16.4
+2 0
2.0 0.5
Note: The carrier tape is compliant to the packaging materials standards for ESD sensitive device, EIA-541
8
Moisture Proof Packaging All HSDL-3220 options are shipped in moisture proof package. Once opened, moisture absorption begins.
This part is compliant to JEDEC Level 4.
Baking Conditions If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts.
Package Temp.
60C 100C 125C 150C Baking should only be done once.
Time
48 hours 4 hours 2 hours 1 hour
UNITS IN A SEALED MOISTURE-PROOF PACKAGE
In reels In bulk
PACKAGE IS OPENED (UNSEALED)
Recommended Storage Conditions
Storage Temperature Relative Humidity
ENVIRONMENT LESS THAN 30C, AND LESS THAN 60% RH
10C to 30C below 60% RH
YES
NO BAKING IS NECESSARY
YES
PACKAGE IS OPENED LESS THAN 72 HOURS
Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within three days if stored at the recommended storage conditions.
NO
PERFORM RECOMMENDED BAKING CONDITIONS
NO
Figure 11. Baking conditions chart.
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Recommended Reflow Profile
255 230 220 200 180 160 120 80 25 0 P1 HEAT UP 50 100 P2 SOLDER PASTE DRY 150 200 P3 SOLDER REFLOW 250 P4 COOL DOWN 300 R1 MAX. 260C R3 R4
T - TEMPERATURE - (C)
R2
60 sec. MAX. ABOVE 220C
R5
t-TIME (SECONDS)
Process Zone
Heat Up Solder Paste Dry Solder Reflow
Symbol
P1, R1 P2, R2 P3, R3 P3, R4
T
25C to 160C 160C to 200C 200C to 255C (260C at 10 seconds max) 255C to 200C 200C to 25C
Maximum T/time
4C/s 0.5C/s 4C/s -6C/s -6C/s
Cool Down
P4, R5
The reflow profile is a straightline representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different T/time temperature change rates. The T/time rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3220 castellation pins are heated to a temperature of 160C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4C per second to allow for even heating of both the PC board and HSDL-3220 castellations.
Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200 C (392 F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255 C (491 F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic
growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200 C (392 F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25 C (77 F) should not exceed 6 C per second maximum. This limitation is necessary to allow the PC board and HSDL-3220 castellations to change dimensions evenly, putting minimal stresses on the HSDL-3220 transceiver.
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Appendix A: SMT Assembly Application Note Solder Pad, Mask and Metal Stencil Aperture
STENCIL APERTURE METAL STENCIL FOR SOLDER PASTE PRINTING
LAND PATTERN
SOLDER MASK
PCB
Figure 12. Stencil and PCBA.
Recommended Land Pattern
C L 1.35 SHIELD SOLDER PAD
MOUNTING CENTER 0.10
1.25 2.05
0.775 1.75
FIDUCIAL 0.60 0.475 1.425 UNIT: mm 2.375 3.325
Figure 13. Stencil and PCBA.
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Recommended Metal Solder Stencil Aperture It is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern.
APERTURES AS PER LAND DIMENSIONS t
w l
Figure 14. Solder stencil aperature.
Stencil thickness, t (mm)
0.152 mm 0.127 mm
Aperture size (mm) length, l width, w
2.60 0.05 3.00 0.05 0.55 0.05 0.55 0.05
Adjacent Land Keepout and Solder Mask Areas Adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. It is recommended that two fiducial crosses be place at midlength of the pads for unit alignment. Note: Wet/Liquid PhotoImageable solder resist/mask is recommended.
10.1
0.2 3.85
SOLDER MASK
3.0
UNITS: mm
Figure 15. Adjacent land keepout and solder mask areas.
12
Appendix B: PCB Layout Suggestion The following PCB layout guidelines should be followed to obtain a good PSRR and EM immunity resulting in good electrical performance. Things to note: 1. The ground plane should be continuous under the part, but should not extend under the shield trace. 2. The shield trace is a wide, low inductance trace back to the system ground. CX1, CX2, CX3, and CX4 are optional supply filter capacitors; they may be left out if a clean power supply is used. 3. Vled can be connected to either unfiltered or unregulated power supply. If Vled and Vcc share the same power supply, CX3 need not be used and the connections for CX1 and CX2 should be before the current limiting resistor R1. In a noisy environment, including capacitor CX2 can enhance supply rejection. CX1 is generally a ceramic capacitor of low inductance providing a wide frequency response while CX2 and CX3 are tantalum capacitors of big volume and fast frequency response. The use of a tantalum capacitor is more critical on the Vled line, which carries a high current. CX4 is an optional ceramic capacitor, similar to CX1, for the IOVcc line.
4. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer underneath and near the transceiver
module as Vcc, and sandwich that layer between ground connected board layers. Refer to the diagram below for an example of a 4 layer board.
TOP LAYER CONNECT THE METAL SHIELD AND MODULE GROUND PIN TO BOTTOM GROUND LAYER.
LAYER 2 CRITICAL GROUND PLANE ZONE. DO NOT CONNECT DIRECTLY TO THE MODULE GROUND PIN. LAYER 3 KEEP DATA BUS AWAY FROM CRITICAL GROUND PLANE ZONE.
BOTTOM LAYER (GND)
The area underneath the module at the second layer, and 3 cm in all directions around the module is defined as the critical ground plane zone. The ground plane should be maximized in this
zone. Refer to application note AN1114 or the Agilent IrDA Data Link Design Guide for details. The layout below is based on a 2-layer PCB.
Figure 16. PCB layout suggestion.
13
Appendix C: General Application Guide for the HSDL-3220 Description The HSDL-3220, a low-cost and small form factor infrared transceiver, is designed to address the mobile computing market such as PDAs, as well as small-embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.4 low power specification from 9.6 kbit/s to 4.0 Mbit/s, and supports HP-SIR and TV Remote modes. The design of the HSDL3220 also includes the following unique features: * Low passive component count. * Shutdown mode for low power consumption requirement. * Interface to input/output logic circuits as low as 1.8V Selection of Resistor R1 Resistor R1 should be selected to provide the appropriate peak pulse LED current over different ranges of Vcc as shown in the table below. Interface to Recommended I/O chips The HSDL-3220's TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6 kbit/s up to 4.0 Mbit/s is available at the RXD pin. The block diagram below shows how the IR port fits into a mobile phone and PDA platform.
Recommended R1
5.6
Vcc
3.0 V
Intensity
45 mW/sr
Minimum Peak Pulse LED Current
150 mA
SPEAKER
AUDIO INTERFACE DSP CORE MICROPHONE
ASIC CONTROLLER RF INTERFACE TRANSCEIVER MOD/ DE-MODULATOR MICROCONTROLLER USER INTERFACE
IR
Figure 17. Mobile phone platform.
HSDL-3220
14
LCD Panel
IR
RAM
ROM
CPU for embedded application
HSDL-3220
PCMCIA Controller
Touch Panel
RS232C Driver
COM Port
Figure 18. PDA platform.
The link distance testing was done using typical HSDL-3220 units with SMC's FDC37C669 and FDC37N769 Super I/O controllers. An IR link distance of up to 50 cm was demonstrated for SIR and FIR speeds.
15
Appendix D: Window Designs for HSDL-3220 Optical port dimensions for HSDL-3220 To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30 and the maximum size corresponds to a cone angle of 60 . In the figure below, X is the width of the window, Y is the height of the window and Z is the distance from the HSDL-3220 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens, K, is 5.1mm. The equations for computing the window dimensions are as follows: X = K + 2*(Z+D)*tanA Y = 2*(Z+D)*tanA The above equations assume that the thickness of the window is negligible compared to the distance of the module from the back of the window (Z). If they are comparable, Z' replaces Z in the above equation. Z' is defined as Z' = Z + t/n where `t' is the thickness of the window and `n' is the refractive index of the window material. The depth of the LED image inside the HSDL-3220, D, is 3.17 mm. `A' is the required half angle for viewing. For IrDA compliance, the minimum is 15 and the maximum is 30 . Assuming the thickness of the window to be negligible, the equations result in the following tables and graphs.
OPAQUE MATERIAL
IR TRANSPARENT WINDOW
Y
X IR TRANSPARENT WINDOW OPAQUE MATERIAL
K
Z A
D
Figure 19. Window design diagram.
16
Module Depth (z) mm
0 1 2 3 4 5 6 7 8 9
Aperture Width (x, mm) Max. Min.
8.76 9.92 11.07 12.22 13.38 14.53 15.69 16.84 18.00 19.15 6.80 7.33 7.87 8.41 8.94 9.48 10.01 10.55 11.09 11.62
Aperture Height (y, mm) Max. Min.
3.66 4.82 5.97 7.12 8.28 9.43 10.59 11.74 12.90 14.05 1.70 2.33 2.77 3.31 3.84 4.38 4.91 5.45 5.99 6.52
APERTURE WIDTH (X) vs. MODULE DEPTH 25
APERTURE HEIGHT (Y) vs. MODULE DEPTH 16
20
APERTURE HEIGHT (Y) - mm
APERTURE WIDTH (X) - mm
14 12 10 8 6 4 2 0 0 1 2 3 4 59 6 Y MAX. Y MIN. 7 8
15
10 X MAX. X MIN.
5 0
0
1
2
3
4
59 6
7
8
MODULE DEPTH (Z) - mm
MODULE DEPTH (Z) - mm
Figure 20. Aperture width (X) vs. module depth.
Figure 21. Aperture height (Y) vs. module depth.
17
Window Material Almost any plastic material will work as a window material. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 875 nm. The recommended plastic materials for use as a cosmetic window are available from General Electric Plastics.
Shape of the Window From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. The amount of change in
the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm.
Recommended Plastic Materials: Material #
Lexan 141 Lexan 920A Lexan 940A
Light Transmission
88% 85% 85%
Haze
1% 1% 1%
Refractive Index
1.586 1.586 1.586
Note: 920A and 940A are more flame retardant than 141.
Flat Window (First Choice)
Figure 22. Shape of windows.
Curved Front and Back (Second Choice)
Curved Front, Flat Back (Do Not Use)
18
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2006 Avago Technologies, Limited. All rights reserved. Obsoletes 5989-3140EN 5989-3640EN August 29, 2006

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